Makefile笔记.

http://stackoverflow.com/questions/3932895/makefile-aliases

SRC=$(wildcard '*.c')

test: $(SRC)
    gcc -o $@ $^ $(CFLAGS) $(LIBS)

    $@ is the target i.e. test
    $^ is the list of pre-requisites for the rule (which in this case is the expanded wild card list as specified in SRC=$(wildcard '*.c'))

    SRC=$(wildcard '*.c')    it's a file matching wildcard. https://www.gnu.org/software/make/manual/html_node/Wildcard-Function.html#Wildcard-Function
    
All such variables are explained in the Automatic variables page of the GNU make manual.
https://www.gnu.org/software/make/manual/html_node/Automatic-Variables.html#Automatic-Variables

a makefile to compile all C source files in the directory and then link them together could be written as follows:

objects := $(patsubst %.c,%.o,$(wildcard *.c))

foo : $(objects)
        cc -o foo $(objects)

$(patsubst %.c,%.o,$(wildcard *.c))    it can  change the list of C source files into a list of object files by replacing the ‘.c’ suffix with ‘.o’ in the result,

$(wildcard *.c)    it can get a list of all the C source files in a directory       

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